1. Field of the Invention
This invention relates to MOS field-effect transistors and a nonvolatile semiconductor memory device using the same, and particularly to those suitable for use in the stacked-gate EEPROM (Electrically Erasable Programmable ROM) and EPROM (Erasable Programmable ROM).
2. Description of Related Art
The conventional MOS field-effect transistor and nonvolatile semiconductor memory device are described in, for example, "16M EPROM cell technology", NIKKEI MICRO DEVICES January, 1990 p.p. 101-107. According to this document, the MOS field-effect transistor and nonvolatile memory device are built up by injecting impurity ions of a second conductivity type into a semiconductor substrate of a first conductivity type, thereby forming a pair of second conductivity type diffusion layers so that the layers are separated from each other by a certain distance, serving as source and drain regions. Therefore, this structure tends to increase the junction depth of the second conductivity type diffusion layers and the channel-wise width of the tunnel window in the overlapped region between the diffusion layer and the gate.
For example, the junction depth of the second conductivity type diffusion layers in the conventional MOS field-effect transistor is 0.2 through 0.3 .mu.m, and the channel-wise width of the tunnel window is 0.05 through 0.1 .mu.m.
In addition, the electrode layers are formed to be made in contact with the parts of the second conductivity type diffusion layers which are in contact with the active region. The channel length is about 0.6 .mu.m in the 16-MB class.
Thus, the conventional MOS field-effect transistor and the nonvolatile semiconductor memory device using the same have the defect that the junction depth of the diffusion layer, the spread of the source-side depletion layer to the drain side and the spread of the drain-side depletion layer to the source side become so great as to cause the punch-through phenomenon easily since the second conductivity diffusion layers are formed as drain and source regions by the ion implantation as described above.
In addition, since the lateral diffusion of second conductivity type diffusion layer is increased with the increase of its junction depth, the tunnel window in the flash EEPROM is extended with the result that the erase efficiency is low. Also, when the lateral diffusion is much spread, the short channel effect may easily occur, thus limiting the minimum channel length. This lower limit of the channel length is disadvantageous to the miniaturization of the transistor elements.
Moreover, since the external electrode is in contact with only a part of the second conductivity type diffusion layer, it is difficult to reduce the contact resistance.
Furthermore, since the second conductivity type diffusion layers are formed by the ion implantation, a crystal defect may easily occur in the diffusion layers.